MPEG video decoder with integrated scaling and display functions

ABSTRACT

A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P &amp; B frames. The full size I and P frames are used to support future decode operations, while the scaled I, P &amp; B frames are retrieved for display.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application contains subject matter which is related to thesubject matter of the following United States patent applications, whichare assigned to the same assignee of this application. Each of the belowlisted applications is hereby incorporated herein by reference:

[0002] “Anti-Flicker Logic For MPEG Video Decoder With IntegratedScaling and Display Functions,” by D. Hrusecky, co-filed herewith, Ser.No. ______, (attorney docket no. EN998143);

[0003] “Multi-Format Reduced Memory MPEG-2 Compliant Decoder,” by Cheneyet al., Ser. No. 08/958,632;

[0004] “Multi-Format Reduced Memory Video Decoder With AdjustablePolyphase Expansion Filter,” by D. Hrusecky, Ser. No. 09/015,463, whichis a continuation-in-part application from pending U.S. patentapplication “Multi-Format Reduced Memory MPEG-2 Compliant Decoder,” byCheney et al., Ser. No. 08/958,632;

[0005] “Multi-Format Reduced Memory MPEG Decoder With Hybrid MemoryAddress Generation,” by Cheney et al., Ser. No. 09/014,896, which is acontinuation-in-part application from pending U.S. patent application“Multi-Format Reduced Memory MPEG-2 Compliant Decoder,” by Cheney etal., Ser. No. 08/958,632; and

[0006] “Compression/Decompression Engine For Enhanced Memory Storage InMPEG Decoder,” by Buerkle et al., Ser. No. 08/971,438.

TECHNICAL FIELD

[0007] The present invention is directed generally to digital videosignal processing, and more particularly, to integrated decode systems,methods and articles of manufacture which allow selective scaling ofvideo presentation by a predetermined reduction factor, while at thesame time allowing for reduced external memory requirements for framebuffer storage.

BACKGROUND OF THE INVENTION

[0008] The MPEG-2 standard describes an encoding method that results insubstantial bandwidth reduction by a subjective lossy compressionfollowed by a lossless compression. The encoded, compressed digital datais subsequently decompressed and decoded in an MPEG-2 compliant decoder.Video decoding in accordance with the MPEG-2 standard is described indetail in commonly assigned U.S. Pat. No. 5,576,765, entitled “VideoDecoder”, which is hereby incorporated herein by reference in itsentirety.

[0009] Video decoders are typically embodied as general or specialpurpose processors and memory. For a conventional MPEG-2 decoder, twodecoded reference frames are typically stored in memory at the sametime. Thus, the cost of memory can often dominate the cost of the decodesystem. For example, an MPEG-2 video decoder might employ 2 MB or moreof external memory, which generally comprises Dynamic Random AccessMemory (DRAM). External memory is used for various data areas, orbuffers such as frame buffers.

[0010] In practice, the MPEG-2 video decoder is typically limited to 2MB of external memory in order to minimize cost of the end product. Thedecoder must perform all of its functions within this limitation. Forexample, of particular importance is enabling output for both theEuropean market which utilizes the PAL standard of 576 video scan linesand the U.S. market which utilizes the NTSC standard of 480 video scanlines. Even if there is no 2 MB of external memory limitation, it isadvantageous to perform the video decode and display in as small amemory space as possible in order to give the remaining memory to otherbuilt-in features, such as on-screen graphics.

[0011] The MPEG-2 decompressed video data buffers, also called framebuffers, consume the largest part of external DRAM, therefore they arethe prime candidate for memory reduction/compression. The frame bufferscontain final pixel display and MPEG-reference data, and hence thereduction technique must also retain high video fidelity.

[0012] As the MPEG video decoder market becomes more and morecompetitive, there is a need for high level of feature integration atthe lowest possible cost to achieve success in the marketplace. One suchfeature that, in the past, would have required circuitry external to thevideo decoder function is video scaling. The kind of scaling desired isto reduce the size of the display picture by a factor, such as 2 or 4,in both the horizontal and vertical axis.

[0013] In view of the above, and in order to establish commercialadvantage, a novel design is desired wherein a video scaling feature isbuilt into the video decoder, such that advantageous use of existingdecoder hardware can be applied to the processes required to produce ahigh quality scaled image. In one principal aspect, the presentinvention addresses this need.

DISCLOSURE OF THE INVENTION

[0014] Briefly summarized, this invention comprises in one aspect avideo decoding system which includes a video decoder for decoding anencoded stream of video data and a decimation unit coupled to the videodecoder. The video decoder produces a decoded stream of video data andthe decimation unit is adapted to scale the decoded stream of video datafor display. The scaling occurs within the video decode system prior tostorage of the decoded stream of video data in a frame buffer.

[0015] In another aspect, the invention comprises a digital videodecoding system which includes a video decoder and a video scalar. Thevideo decoder decodes an encoded stream of video data and producestherefrom a decoded stream of video data. The video scalar is coupled tothe video decoder for scaling the decoded stream of video data prior tostorage thereof in a frame buffer. The video decoding system includes anormal video mode and a scaled video mode. The video scalar scales thedecoded stream of video data when the digital video decoding system isin the scaled video mode. The digital video decoding system furtherincludes display mode switch logic for switching between the normalvideo mode and the scaled video mode, wherein the switching occurswithout perceptual degradation of the display of the decoded stream ofvideo data.

[0016] In yet another aspect, a digital video decoding system isprovided having a normal video mode and a scaled video mode. When in thenormal video mode, full size frames are output for display on a videodisplay coupled to the digital video decoding system, and when in thescaled video mode, scaled frames comprising a fractional size of thefull size frames are output for display on the video display. A framebuffer is provided for temporarily storing the full size frames and thescaled frames after a decoding time thereof and prior to a display time,wherein there is a predefined latency between the decoding time and thedisplay time. The predefined latency between the decoding time and thedisplay time comprises a first latency when the digital video decodingsystem is in normal video mode and a second latency when the digitalvideo decoding system is in scaled video mode.

[0017] In still another aspect, a frame buffer is provided for a digitalvideo decoding system having video scaling capabilities. The framebuffer includes multiple defined memory areas for receiving I, P & Bframes of a decoded stream of video data. The multiple defined memoryareas comprise a first area and a second area for receiving full size Iand P frames of the decoded stream of video data, as well as at leastone third area for receiving scaled I, P & B frames of the decodedstream of video data commensurate with the first area and the secondarea receiving the full size I and P frames.

[0018] In a further aspect, the invention comprises a frame buffer for adigital video decoding system having video scaling capabilities. Theframe buffer includes memory associated with the digital video decodingsystem. The memory is of a predefined size. The frame buffer furtherincludes control logic for partitioning the memory of the predefinedsize into three buffer areas when the digital video decoding system isin a normal video mode, wherein the three buffer areas receive full sizeI, P & B frames of a decoded stream of video data. The control logic isfurther adapted to partition the memory into five buffer areas when thedigital video decoding system is in a scaled video mode. The five bufferareas comprise a first area and a second area for receiving full size Iand P frames of the decoded stream of video data, and at least a thirdarea, fourth area and fifth area for receiving scaled I, P & B frames ofthe decoded stream of video data.

[0019] Methods and articles of manufacture corresponding to theabove-outlined systems and frame buffers are also described and claimedherein.

[0020] To restate, disclosed herein is a digital video decode system,method and article of manufacture which present an integrated scalingcapability. The decoder is arranged such that it reduces the overallbandwidth to external memory when in the scaling mode. For example, thedisplay picture can be reduced by a factor of 2 and/or 4 in both thehorizontal and vertical axis. Advantageously, the integrated scalingfunction for the video decode system presented herein uses existingdecoder hardware to produce a high quality scaled image.

[0021] By performing decimation/scaling at decode time, the total memorybandwidth requirement is reduced, making more memory bandwidth availableto other features, such as onscreen graphics. Thus, scaling implementedin accordance with this invention requires less external memory (i.e.,frame buffer memory) than would be required by a post-processingapproach, i.e., a display scaler would require four full size framebuffers. Further, in accordance with this invention, switching betweennon-scaling and scaling modes does not produce display artifacts.Scaling in accordance with this invention can also be employed with Bframe memory reduction in full frame format, as well as with letterboxformat.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above-described objects, advantages and features of thepresent invention, as well as others, will be more readily understoodfrom the following detailed description of certain preferred embodimentsof the invention, when considered in conjunction with the accompanyingdrawings in which:

[0023]FIG. 1 shows an exemplary pair of groups of pictures (GOPs);

[0024]FIG. 2 shows an exemplary macroblock (MB) subdivision of a picture(4:2:0 format);

[0025]FIG. 3 depicts a block diagram of a video decoder;

[0026]FIG. 4 is block diagram of a video decoding system to employ theprinciples of the present invention;

[0027]FIG. 5 is a detailed embodiment of a video decoding system inaccordance with the principles of the present invention;

[0028]FIG. 6 illustrates frame buffer subdivision in a normal mode andin a video scaling mode in accordance with the present invention;

[0029]FIG. 7a is a timing diagram showing delayed display timing in avideo scaling mode in accordance with the principles of the presentinvention;

[0030]FIG. 7b illustrates one example of switching of the small framebuffers 2, 4 & 6 of FIG. 6 in accordance with the present invention;

[0031]FIG. 8 is a block diagram of one embodiment of a decimation unitin accordance with the principles of the present invention for the videodecode system of FIG. 5;

[0032]FIG. 9 is a block diagram of one embodiment of display mode switchlogic in accordance with the principles of the present invention for thevideo decode system of FIG. 5; and

[0033]FIG. 10 is a flowchart of one embodiment of processing implementedby the sync generator of FIG. 9 in accordance with the principles of thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0034] As the present invention may be applied in connection with anMPEG-2 decoder, in order to facilitate an understanding of theinvention, some pertinent aspects of the MPEG-2 compression algorithmare first reviewed. It is to be noted, however, that the invention canalso be applied to other video coding algorithms which share some of thefeatures of the MPEG-2 algorithm.

[0035] To begin with, it will be understood that the compression of adata object, such as a page of text, an image, a segment of speech, or avideo sequence, can be thought of as a series of steps, including: 1) adecomposition of that object into a collection of tokens; 2) therepresentation of those tokens by binary strings which have minimallength in some sense; and 3) the concatenation of the strings in awell-defined order. Steps 2 and 3 are lossless, i.e., the original datais faithfully recoverable upon reversal, and Step 2 is known as entropycoding. Step 1 can be either lossless or lossy in general. Most videocompression algorithms are lossy because of stringent bitraterequirements. A successful lossy compression algorithm eliminatesredundant and irrelevant information, allowing relatively large errorswhere they are not likely to be visually significant and carefullyrepresenting aspects of a sequence to which the human observer is verysensitive. The techniques employed in the MPEG-2 algorithm for Step 1can be described as predictive/interpolative motion-compensated hybridDCT/DPCM coding. Huffman coding, also known as variable length coding,is used in Step 2.

[0036] The MPEG-2 video standard specifies a coded representation ofvideo for transmission as set forth in ISO-IEC JTC1/SC29/WG11, GenericCoding of Moving Pictures and Associated Audio Information: Video,International Standard, 1994. The algorithm is designed to operate oninterlaced or non-interlaced component video. Each picture has threecomponents: luminance (Y), red color difference (Cr), and blue colordifference (Cb). The video data may be coded in 4:4:4 format, in whichcase there is one Cr and one Cb sample for each Y sample, in 4:2:2format, in which case there are half as many Cr and Cb samples asluminance samples in the horizontal direction, or in 4:2:0 format, inwhich case there are half as many Cr and Cb samples as luminance samplesin both the horizontal and vertical directions.

[0037] An MPEG-2 data stream consists of a video stream and an audiostream which are packed, together with systems information and possiblyother bitstreams, into a systems data stream that can be regarded aslayered. Within the video layer of the MPEG-2 data stream, thecompressed data is further layered. A description of the organization ofthe layers will aid in understanding the invention. These layers of theMPEG-2 Video Layered Structure are shown in FIGS. 1 & 2. The layerspertain to the operation of the compression algorithm as well as thecomposition of a compressed bit stream. The highest layer is the VideoSequence Layer, containing control information and parameters for theentire sequence. At the next layer, a sequence is subdivided into setsof consecutive pictures, each known as a “Group of Pictures” (GOP). Ageneral illustration of this layer is shown in FIG. 1. Decoding maybegin at the start of any GOP, essentially independent of the precedingGOPs. There is no limit to the number of pictures which may be in a GOP,nor do there have to be equal numbers of pictures in all GOPs.

[0038] The third or Picture layer is a single picture. A generalillustration of this layer is shown in FIG. 2. The luminance componentof each picture is subdivided into 16×16 regions; the color differencecomponents are subdivided into appropriately sized blocks spatiallyco-sited with the 16×16 luminance regions; for 4:4:4 video, the colordifference components are 16×16, for 4:2:2 video, the color differencecomponents are 8×16, and for 4:2:0 video, the color differencecomponents are 8×8. Taken together, these co-sited luminance region andcolor difference regions make up the fifth layer, known as a“macroblock” (MB). Macroblocks in a picture are numbered consecutivelyin lexicographic order, starting with Macroblock 1.

[0039] Between the Picture and MB layers is the fourth or “slice” layer.Each slice consists of some number of consecutive MB's. Finally, each MBconsists of four 8×8 luminance blocks and 8, 4, or 2 (for 4:4:4, 4:2:2and 4:2:0 video) chrominance blocks. The Sequence, GOP, Picture, andslice layers all have headers associated with them. The headers beginwith byte-aligned Start Codes and contain information pertinent to thedata contained in the corresponding layer.

[0040] A picture can be either field-structured or frame-structured. Aframe-structured picture contains information to reconstruct an entireframe, i.e., the combination of one field containing the odd lines andthe other field containing the even lines. A field-structured picturecontains information to reconstruct one field. If the width of eachluminance frame (in picture elements or pixels) is denoted as C and theheight as R (C is for columns, R is for rows), a field-structuredpicture contains information for C×R/2 pixels.

[0041] The two fields in a frame are the top field and the bottom field.If we number the lines in a frame starting from 1, then the top fieldcontains the odd lines (1, 3, 5, . . . ) and the bottom field containsthe even lines (2, 4, 6, . . . ). Thus we may also call the top fieldthe odd field, and the bottom field the even field.

[0042] A macroblock in a field-structured picture contains a 16×16 pixelsegment from a single field. A macroblock in a frame-structured picturecontains a 16×16 pixel segment from the frame that both fields compose;each macroblock contains a 16×8 region from each of the two fields.

[0043] Within a GOP, three types of pictures can appear. Thedistinguishing difference among the picture types is the compressionmethod used. The first type, Intramode pictures or I-pictures, arecompressed independently of any other picture. Although there is nofixed upper bound on the distance between I-pictures, it is expectedthat they will be interspersed frequently throughout a sequence tofacilitate random access and other special modes of operation.Predictively motion-compensated pictures (P pictures) are reconstructedfrom the compressed data in that picture plus two reconstructed fieldsfrom previously displayed I or P pictures. Bidirectionallymotion-compensated pictures (B pictures) are reconstructed from thecompressed data in that picture plus two reconstructed fields frompreviously displayed I or P pictures and two reconstructed fields from 1or P pictures that will be displayed in the future. Becausereconstructed I or P pictures can be used to reconstruct other pictures,they are called reference pictures.

[0044] With the MPEG-2 standard, a frame can be coded either as aframe-structured picture or as two field-structured pictures. If a frameis coded as two field-structured pictures, then both fields can be codedas I pictures, the first field can be coded as an I picture and thesecond field as a P picture, both fields can be coded as P pictures, orboth fields can be coded as B pictures.

[0045] If a frame is coded as a frame-structured I picture, as twofield-structured I pictures, or as a field-structured I picture followedby a field-structured P picture, we say that the frame is an I frame; itcan be reconstructed without using picture data from previous frames. Ifa frame is coded as a frame-structured P picture or as twofield-structured P pictures, we say that the frame is a P frame; it canbe reconstructed from information in the current frame and thepreviously coded I or P frame. If a frame is coded as a frame-structuredB picture or as two field-structured B pictures, we say that the frameis a B frame; it can be reconstructed from information in the currentframe and the two previously coded I or P frames (i.e., the I or Pframes that will appear before and after the B frame). We refer to I orP frames as reference frames.

[0046] A common compression technique is transform coding. In MPEG-2 andseveral other compression standards, the discrete cosine transform (DCT)is the transform of choice. The compression of an I-picture is achievedby the steps of 1) taking the DCT of blocks of pixels, 2) quantizing theDCT coefficients, and 3) Huffman coding the result. In MPEG-2, the DCToperation converts a block of n×n pixels into an n×n set of transformcoefficients. Like several of the international compression standards,the MPEG-2 algorithm uses a DCT block size of 8×8. The DCTtransformation by itself is a lossless operation, which can be invertedto within the precision of the computing device and the algorithm withwhich it is performed.

[0047] The second step, quantization of the DCT coefficients, is theprimary source of lossiness in the MPEG-2 algorithm. Denoting theelements of the two-dimensional array of DCT coefficients by cmn, wherem and n can range from 0 to 7, aside from truncation or roundingcorrections, quantization is achieved by dividing each DCT coefficientcmn by wmn times QP, with wmn being a weighting factor and QP being thequantizer parameter. The weighting factor wmn allows coarserquantization to be applied to the less visually significantcoefficients. The quantizer parameter QP is the primary means of tradingoff quality vs. bit-rate in MPEG-2. It is important to note that QP canvary from MB to MB within a picture.

[0048] Following quantization, the DCT coefficient information for eachMB is organized and coded, using a set of Huffman codes. As the detailsof this step are not essential to an understanding of the invention andare generally understood in the art, no further description is neededhere.

[0049] Most video sequences exhibit a high degree of correlation betweenconsecutive pictures. A useful method to remove this redundancy prior tocoding a picture is “motion compensation”. MPEG-2 provides tools forseveral methods of motion compensation.

[0050] The methods of motion compensation have the following in common.For each macroblock, one or more motion vectors are encoded in the bitstream. These motion vectors allow the decoder to reconstruct amacroblock, called the predictive macroblock. The encoder subtracts the“predictive” macroblock from the macroblock to be encoded to form the“difference” macroblock. The encoder uses tools to compress thedifference macroblock that are essentially similar to the tools used tocompress an intra macroblock.

[0051] The type of a picture determines the methods of motioncompensation that can be used. The encoder chooses from among thesemethods for each macroblock in the picture. If no motion compensation isused, the macroblock is intra (I). The encoder can make any macroblockintra. In a P or a B picture, forward (F) motion compensation can beused; in this case, the predictive macroblock is formed from data in theprevious I or P frame. In a B picture, backward (B) motion compensationcan also be used; in this case, the predictive macroblock is formed fromdata in the future I or P frame. In a B picture, forward/backward (FB)motion compensation can also be used; in this case, the predictivemacroblock is formed from data in the previous I or P frame and thefuture I or P frame.

[0052] Because I and P pictures are used as references to reconstructother pictures (B and P pictures) they are called reference pictures.Because two reference frames are needed to reconstruct B frames, MPEG-2decoders typically store two decoded reference frames in memory.

[0053] Aside from the need to code side information relating to the MBmode used to code each MB and any motion vectors associated with thatmode, the coding of motion-compensated macroblocks is very similar tothat of intramode MBs. Although there is a small difference in thequantization, the model of division by wmn times QP still holds.

[0054] The MPEG-2 algorithm can be used with fixed bit-rate transmissionmedia. However, the number of bits in each picture will not be exactlyconstant, due to the different types of picture processing, as well asthe inherent variation with time of the spatio-temporal complexity ofthe scene being coded. The MPEG-2 algorithm uses a buffer-based ratecontrol strategy to put meaningful bounds on the variation allowed inthe bit-rate. A Video Buffer Verifier (VBV) is devised in the form of avirtual buffer, whose sole task is to place bounds on the number of bitsused to code each picture so that the overall bit-rate equals the targetallocation and the short-term deviation from the target is bounded. Thisrate control scheme can be explained as follows. Consider a systemconsisting of a buffer followed by a hypothetical decoder. The buffer isfilled at a constant bit-rate with compressed data in a bit stream fromthe storage medium. Both the buffer size and the bit-rate are parameterswhich are transmitted in the compressed bit stream. After an initialdelay, which is also derived from information in the bit stream, thehypothetical decoder instantaneously removes from the buffer all of thedata associated with the first picture. Thereafter, at intervals equalto the picture rate of the sequence, the decoder removes all dataassociated with the earliest picture in the buffer.

[0055]FIG. 3 shows a diagram of a conventional video decoder.

[0056] The compressed data enters as signal 11 and is stored in thecompressed data memory 12. The variable length decoder (VLD) 14 readsthe compressed data as signal 13 and sends motion compensationinformation as signal 16 to the motion compensation (MC) unit 17 andquantized coefficients as signal 15 to the inverse quantization (IQ)unit 18. The motion compensation unit reads the reference data from thereference frame memory 20 as signal 19 to form the predicted macroblock,which is sent as the signal 22 to the adder 25. The inverse quantizationunit computes the unquantized coefficients, which are sent as signal 21to the inverse transform (IDCT) unit 23. The inverse transform unitcomputes the reconstructed difference macroblock as the inversetransform of the unquantized coefficients. The reconstructed differencemacroblock is sent as signal 24 to the adder 25, where it is added tothe predicted macroblock. The adder 25 computes the reconstructedmacroblock as the sum of the reconstructed difference macroblock and thepredicted macroblock. The reconstructed macroblock is then sent assignal 26 to the demultiplexer 27, which stores the reconstructedmacroblock as signal 29 to the reference memory if the macroblock comesfrom a reference picture or sends it out (to memory or display) assignal 28. Reference frames are sent out as signal 30 from the referenceframe memory.

[0057] Various techniques have been proposed for reducing memoryrequirements of a decode system by storing decoded video data incompressed form. One such technique is described in theabove-incorporated patent application entitled “Multi-Format ReducedMemory MPEG-2 Compliant Decoder,” Ser. No. 08/958,632. This co-pendingapplication relates to a method for reducing memory requirements forframe buffer storage for an MPEG-2 decoder, and to editing or modifyingthe video output, e.g., from a 4:3 form factor of television to a 16:9format of motion pictures. A significant aspect of the technique isdecimation of the B-coded pictures within hardware of the video decoder.This technique includes first motion compensating the P-coded andB-coded pictures, followed by decimating the B-coded pictures during thedecode phase, and increasing the size of scan line fetches for theI-coded and P-coded pictures to enable their horizontal decimationduring the display phase.

[0058] A decode system, generally denoted 40, to employ the presentinvention is depicted in FIG. 4. System 40 includes a bus interface 44which couples the decode system 40 to a memory bus 42. MPEG encodedvideo data is fetched from PCI bus 42 by a DMA controller 46 whichwrites the data to a video First-In/First-Out (FIFO) buffer 48. The DMAcontroller also fetches on-screen display and/or audio data from bus 42for writing to an OSD/audio FIFO 50. A memory controller 52 will placevideo data into a correct memory buffer within dynamic random accessmemory (DRAM) 53. MPEG compressed video data is then retrieved by thevideo decoder 54 from DRAM 53 and decoded as described above inconnection with FIG. 3. Conventionally, the decoded video data is thenstored back into the frame buffers of DRAM 53 for subsequent use asalready described. When a reference frame is needed, or when video datais to be output from the decode system, stored data in DRAM 53 isretrieved by the MEM controller and forwarded for output via a display &OSD interface 58. Audio data, also retrieved by the memory controller52, is output through an audio interface 60.

[0059] As discussed initially herein, this invention addresses the needfor a decoding system with integrated scaling capability which can scalethe size of an MPEG-2 video presentation by a predetermined reductionfactor. At the same time, the invention preferably allows for reductionin external memory requirements for full-frame buffer storage as well,e.g., using the above-described B frame memory reduction technique. Asthe MPEG-2 video decoder market becomes more and more competitive, theneed for high level of feature integration at the lowest possible costis important to achieving success in the marketplace. The presentinvention acknowledges this by providing a scaling mode to reduce thesize of a display picture by a predefined factor, such as 2 and/or 4 inboth the horizontal and vertical axis.

[0060]FIG. 5 depicts one embodiment of a video decode system inaccordance with the principles of the present invention. This videodecode system includes external memory 53, which in the embodiment showncomprises SDRAM frame buffer storage. Memory 53 interfaces with a memorycontrol unit 52. Memory control unit 52 receives decoded video data froma video decoder 54 and provides video data for display through videodisplay unit 90. In accordance with the principles of the presentinvention, video decode system 65 of FIG. 5 includes numerous featureswhich implement a video scaling mode capability.

[0061] For example, decimation unit 82 is modified to include both anormal video decimation mode and a video scaling mode. Frame buffers 53are modified to accommodate storage of decoded video data in eitherfull-frame format or a combination of full-frame format and scaled videoformat. Display mode switch logic 96 is provided within video displayunit 90 to facilitate seamless switching between normal video mode andscaled video mode. Frame buffer pointer control 86 is modified toprovide the correct frame buffer pointers based on the novelpartitioning of the frame buffers when in normal video mode and when inscaled video mode. Further, as described in the above-incorporated,co-filed United States patent application, a flicker reduction mechanismis preferably integrated within video display unit 90, and in particularwithin vertical upsample logic 94. Each of these features is describedin detail below, with the exception of flicker reduction which isdescribed in the co-filed application.

[0062] Operationally, an MPEG input video source is fed through memorycontrol unit 52 as coded MPEG-2 video data to the input of video decoder54. Decoder 54 includes a Huffman decoder 72, Inverse Quantizer 74,Inverse DCT 76, Motion Compensation 78 and adder 80, which function asdescribed above in connection with the video decoder of FIG. 3. Aninternal processor 70 oversees the video decode process and, inaccordance with the principles of the present invention, receives asignal from a host system whenever the host desires to switch the videodisplay between, for example, normal video display and scaled videodisplay. This signal is referred to in FIG. 5 as a “host controlledformat change” signal. In response to host format changes, controlsignals are sent from internal processor 70 to Huffman decoder 72,Inverse Quantizer 74, Motion Compensation 78, as well as to upsamplelogic 94, display fetch unit 92 and display mode switch logic 96 withinvideo display 90. Again, these control signals direct the video decodesystem in accordance with the principles of the present invention (andas described below) to switch the display output between, for example,normal video mode and scaled video mode.

[0063] Full size macroblocks of decoded video data are sequentiallyoutput from video decoder 54 to decimation unit 82 where, in oneembodiment, the full size macroblocks undergo one of two types ofcompression. First, if full size video is desired, then decimation ofthe B-coded pictures only is still preferably performed as described inthe above-incorporated application entitled: “Multi-Format ReducedMemory MPEG-2 Compliant Decoder”. In this normal video mode, decimationis a process of reducing the amount of data by interpolating oraveraging combined values to get an interpolated pixel value.Interpolation reduces the number of pixels, and therefore, less externalmemory is required in the overall system. In a second mode, decimationunit 82 performs picture scaling in accordance with the principles ofthis invention. By way of example, the type of scaling employed mayreduce the overall size of the display picture by a factor of 2 or 4 inboth the horizontal and vertical axis.

[0064] Along with providing decimation unit 82 with a stream of decodedfull-size macroblocks, video decoder also sends a “motion compensationunit block complete” signal on line 83, which lets decimation unit 82know when a macroblock has been completely decoded. Similarly,decimation unit 82 provides a “decimator busy” signal on line 85 tomotion compensation unit 78 of video decoder 54. This “decimator busy”signal informs the motion compensation unit when the decimation unit isbusy and when the unit has completed its operations, after which themotion compensation unit can proceed to the next macroblock.

[0065] Motion compensation unit 78 of video decoder 54 provides readvideo addresses directly to memory control unit 52, and write videoaddresses to decimation unit 82 for writing of decoded video data (fullsize) and/or scaled macroblocks to external memory 53. In parallel withthe read video address and write video address, pointers are provided byframe buffer pointer control 86 to the memory control unit. Thesepointers define which frame buffer areas within SDRAM 53 are to beaccessed by a given read video address or write video address inaccordance with the partitionings of the frame buffer memory spacepursuant to this invention (as described further below). These pointersare referred to in FIG. 5 as current pointer and current small pointer,with current pointer comprising a pointer for a full size macroblock,and current small pointer comprising a pointer for a scaled macroblock.

[0066] Decimation unit 82 receives the decoded full-size macroblocks,buffers the information internally and if scaling mode is activated,performs scaling as described below. In a normal mode, decimation unit82 outputs decoded video data full-size macroblocks to memory controlunit 52 for storage in frame buffers 53. When in scaling mode,decimation unit 82 scales the full-size macroblocks and outputs scaledmacroblocks to memory control unit 52 for storage in frame buffers 53.

[0067] Frame buffer pointer control 86 is significant and controlsrotation of the frame buffers, i.e., frame buffer assignments, when innormal video mode and video scaling mode in accordance with theprinciples of the present invention (described further below).

[0068] As described in the above-incorporated applications, decimationunit 82 also functions as part of video display unit 90 when retrievingdata for display. Specifically, decoded video data comprising full-sizescan lines is retrieved from frame buffer storage 53 and fed throughdecimation unit 82 for B-frame re-expansion of pictures as explained inthe above-incorporated patent application entitled “Multi-Format ReducedMemory Video Decoder With Adjustable Polyphase Expansion Filter.” Thisis done so that consistency is maintained for the video within a groupof pictures, and thus reduced resolution of any one picture is notperceptible. After re-expansion, the full-size scan lines are providedto display output interface 98.

[0069] Alternatively, when in video scaling mode, decoded videocomprising scaled scan lines is retrieved from frame buffer storage 53and fed directly to scan line video buffers 84. The scan lines aredivided between luminance and chrominance data and both a current scanline and a prior scan line are fed from scan line video buffers 84 tovertical and horizontal upsample logic 94. Upsample controls arereceived from display fetch unit 92, which coordinates letterboxformatting, SIF upsampling, 4:2:0 to 4:2:2 upsampling, and flickerreduction (in accordance with the principles of the above-incorporated,co-filed patent application).

[0070] Display fetch unit 92 provides the read video address forretrieval of scan lines from frame buffer storage 53. A “currentpointer, current small pointer” synchronization (sync) signal fordisplay is received by memory control unit 52 from display mode switchlogic 96 of video display unit 90. As noted above, the current pointer,current small pointer signal points to the particular frame buffer areafrom which scan lines are to be retrieved, while the read video addresssignal designates the particular scan lines to be retrieved within thatframe buffer area.

[0071] Display mode switch logic 96 is provided in accordance with theprinciples of the present invention in order to ensure seamlessswitching between, for example, scaled video mode and normal video mode.Logic 96 receives as input a control signal from internal processor 70of video decoder 54, as well as a vertical synchronization (VSYNC)signal (from display output interface 98) and a B picture “MPEG-2 repeatfield” signal from Huffman decoder 72 of video decoder 54. VSYNC is anexternal synchronization signal that indicates the start of a newdisplay field. Output from display mode switch logic 96, in addition tothe current pointer, current small pointer sync for the display, is a“display format sync for display” signal fed to display fetch unit 92,as well as a “display format sync for decode” signal fed to the decodelogic of decimation unit 82. Display mode switch logic 96 also outputs a“block video” signal to display output interface 98 which is employed,in accordance with the principles of the present invention, to block onedisplay frame to keep noise from the display when switching betweendisplay modes. Video data is received at the display output interfacefrom upsample logic 94. The decimation unit, frame buffer partitioning,frame buffer pointer control and display mode switch logic, allimplemented in accordance with the principles of this invention, aredescribed in greater detail below with reference to FIGS. 6-10.

[0072] First, the frame buffers. The frame buffers are used to store theconstructed pictures for display, as well as for prediction ofsubsequent pictures. Since a B picture is not used for prediction, itsframe buffer is available for use after the picture has been displayed.For I or P pictures, the frame buffer needs to be held after display,particularly for predicting B pictures.

[0073]FIG. 6 depicts frame buffer allocation for both normal video modeand scaled video mode in accordance with the principles of thisinvention. In normal mode, there are three frame buffers to support thedecoding and display processes. Frame buffer 0 and frame buffer 1 areallocated for 1 and P pictures, while frame buffer 2 is assigned to Bpictures. The frame buffers are tagged by buffer pointers, i.e., thecurrent pointers from frame buffer pointer control 86 of FIG. 5.

[0074] In the scaled video mode, at least five frame buffers areemployed. Frame buffer 0 and frame buffer 1 again accommodate full sizeI and P picture video. The at least three other buffers, which arelabeled frame buffer 2, frame buffer 4 and frame buffer 6 in the exampleshown, are tagged by small pointers generated by the frame bufferpointer control. These small buffers are mainly used for displaypurposes when in scaled video mode. The buffers are small size in orderto fit the video scalings. When decoding an I or P picture, theconstructed picture is stored into either buffer 0 or buffer 1 dependingupon whichever is available. At the same time, a scaled down version ofthe same picture is stored into one of the smaller buffers, i.e., framebuffer 2, frame buffer 4 or frame buffer 6. The full size video is thenused for prediction, while the small sized video in the small framebuffers is used for display of the scaled down picture.

[0075] The frame buffers are configured by microcode duringinitialization of the video decode system. A memory base address isassigned to each frame buffer, and these memory base addresses areselected by the buffer pointers generated by frame buffer pointercontrol. The read and write video addresses refer to specific addresseswithin a selected frame buffer. Unless otherwise indicated, the term“frame buffer” is used herein below as inclusive of all frame buffermemory configured during initialization. “Frame buffer area” refers toone of the specific frame buffers depicted in FIG. 6.

[0076] The video display operates in real time, and therefore, framebuffer pointers must be switched according to the VSYNC timing. Sincedecoding is always ahead of the display, a frame buffer must be madeavailable to store the decoded picture. Therefore, the frame bufferpointers must be switched before decoding starts. To avoid thedisturbance to the display frame buffer, a copy of the display bufferpointer is maintained. The buffer switching time is at the beginning ofeach picture decode. The display buffer pointer is also changed at thattime, however, it will not be used until copy display pointer time whichis the beginning of picture display. One embodiment of normal modebuffer pointer rotation is described below.

[0077] The following assumes four buffer pointers, with each pointercontaining two bits to indicate which one of the three frame buffers(buffer 0, 1 and 2) is being accessed.

[0078] current pointer—indicates the frame buffer to be used for theconstructing picture;

[0079] display pointer—indicates the frame buffer to be used for thedisplay;

[0080] future pointer—indicates the frame buffer to be used for thebackward prediction; and

[0081] past pointer—indicates the frame buffer to be used for theforward prediction.

[0082] At startup, the future pointer is initialized to “1” and theother pointers are set to “0”. At the beginning of an I or P picturedecode, the value from the past pointer is loaded into the currentpointer and the value from the future pointer is loaded into the displaypointer. The values in the future pointer and the past pointer areswapped. If the decoding picture is a B picture, the current pointer andthe display pointer are set to “2”. Frame buffer 2 is reserved, in oneexample, for the B pictures. The future pointer and past pointer remainunchanged. Pointer switching in normal mode is described in greaterdetail in U.S. Pat. No. 5,668,599 by Cheney et al., entitled “MemoryManagement For An MPEG-2 Compliant Decoder,” the entirety of which ishereby incorporated herein by reference.

[0083] In scaled video mode, the display time of a picture is delayed byan additional field time in accordance with the present invention. Thepurpose of this delay is to decouple the decode and the displayprocesses so that the decoded scaled video can be placed anywhere on thescreen. FIG. 7a depicts one example of the delayed display timing inscaled video mode. This display timing is adjusted dynamically accordingto the mode, i.e., whether normal mode or scaled video mode. The onefield time delay is needed in accordance with this invention to properlymanage the buffers. At least five buffers are again assumed in the videoscaling mode. As described above, two of these five buffers comprisefull-size frame buffers, and are labeled frame buffer 0 and frame buffer1 in FIG. 6. These full-size frame buffers are the same as thecorresponding buffers used in normal video mode. The at least threesmall frame buffers, i.e., frame buffer 2, frame buffer 4 and framebuffer 6, are allocated in the same memory space occupied by framebuffer 2 used in the normal video mode. These three small frame buffersare controlled by a different algorithm than described above.

[0084] Specifically, four additional pointers are used in scaled videomode. These pointers are:

[0085] small current pointer—indicates a small buffer for the decimatedconstructing picture;

[0086] small display pointer—indicates a small buffer for the display;

[0087] small future pointer—indicates the small buffer for the futuredisplay; and

[0088] small transition pointer—indicates the small buffer for thetransition.

[0089] When the decoder is initialized, the small current pointer, smalldisplay pointer, small future pointer and small transition pointer areset to 0, 2, 4 and 6, respectively. At the start of each picturedecoding, the small current pointer is loaded from the small transitionpointer and the small transition pointer is loaded from the smalldisplay pointer. If the decoding picture is a B picture, then the smalldisplay pointer is loaded from the small transition pointer and thesmall future pointer remains unchanged. If the decoding picture is an Ior P picture, the small display pointer is loaded from the small futurepointer and the small future pointer is loaded from the small transitionpointer. One example of small frame buffer switching in accordance withthe present invention is depicted in FIG. 7b.

[0090] The full-size frame buffers, frame buffer 0 and frame buffer 1,are switching as if the decoder is running in normal mode. These twobuffers are needed for prediction, but are not for display in scaledvideo mode. When an I or P picture is being decoded, the picture isstored in both buffers indicated by the current (full frame) pointer andthe small current pointer. During a B picture decoding, frame buffer 2indicated by the current (full frame) pointer will not be used. Only thesmall frame buffer identified by the small current pointer is used forthe decimated picture. In normal mode, the display pointer is used fordisplay, while in scaled video mode, the small display pointer is used.The two buffer switching algorithms operate simultaneously at thebeginning of each picture decoding. The buffer pointers are simplyselected depending upon which mode the decoder is in.

[0091] Next, FIG. 8 depicts one embodiment of a decimation unit 82 (FIG.5) employed in accordance with the present invention.

[0092] In previous implementations of the decode decimation unit, e.g.,described in the above-incorporated patent application entitled“Multi-Format Reduced Memory MPEG-2 Compliant Decoder”, the decimationunit was limited to operating on B pictures only, for either letterboxor memory reduction purposes. In a scaled video mode as presentedherein, however, the decode decimation unit processes all picture types.This is desirable in order to save memory bandwidth at display time,since (in one embodiment) scaled pictures and multi-plane, highresolution OSD graphics may be mixed at the output.

[0093] In the embodiment of FIG. 8, the decimation unit includesdecimation logic 200, which receives the decoded video data from thevideo decoder and outputs a decimated data flow to a decimation buffer220. Output from decimation buffer 220 is multiplexed 230 with theundecimated, decoded video data received from the video decoder suchthat multiplexer 230 outputs the decoded video data, as well as thescaled macroblocks for storage in frame buffers 0, 1, 2, 4 and 6 asdescribed above when in scaled video mode. The write video address fromthe motion compensation unit of the video decoder is fed to memory writecontrols 240 within the decimation unit, which control writing of datafrom decimation buffer 220. The write video addresses, either with orwithout decimation scaling, are also output through a multiplexer 250 tothe memory control unit (see FIG. 5).

[0094] Multiplexers 230 & 250 are controlled by decimate control signals210. The decimate control logic receives as input a signal called“MCU_block_complete” from the motion compensation unit of the videodecoder. This signal indicates when the decimator can begin to write thescaled macroblock. The decimator informs the motion compensation unitthat it is currently busy through a signal labeled “decimator_busy”.

[0095] For a given macroblock, there are two phases. One phase is forthe luminance, and the other phase is for chrominance. Each phaserequires a write of one full-sized macroblock and one scaled macroblock,again, assuming scaled video mode.

[0096] Various specific changes to the decimation hardware/processdescribed in the above-incorporated “Multi-Format Reduced Memory MPEG-2Compliant Decoder” application are intended herein. One change in thedata flow of the decimation process is the addition (in one example) ofa 4 to 1 horizontal reduction, which is implemented in the horizontaldecimate function of the decimation logic. This is to support {fraction(1/16)} size scaling.

[0097] Another, change is to increase the decimation buffer size to32×32 bits. As I and P pictures are processed, the full-sized macroblockis written to memory, while the decimator scales down the macroblock atthe same time and stores a small macroblock in the decimation buffer220. After the full-sized macroblock is written to memory, the decimatorwrites the scaled macroblock to another buffer location within memory(i.e., frame buffer 2, frame buffer 4 or frame buffer 6 in the exampleabove). The larger decimation buffer allows for the storing of the smallmacroblock.

[0098] The decimate state machine logic is also changed to allow twomodes of operation, i.e., again assuming a scaled video mode. The firstmode is B picture processing and the second mode is reference pictureprocessing. For B picture processing, only the small macroblocks arewritten to memory through decimation buffer 220. The data is pacedthrough the decimation unit as fast as the motion compensation unit candeliver it, since the decimation buffer can hold a complete scaledmacroblock. For reference picture operations, the full-size macroblocksare written to memory first through multiplexer 230, followed by thewriting of the scaled macroblocks. This requires the data flow to bepaced by the memory control unit responding to requests for writing.

[0099] Since the size of the source compressed image may vary, there areexceptions to the above process. The decimator is only required if sometype of reduction is needed to form a scaled picture. Certain videosources will already be small in size, and one dimension, or bothdimensions may not require scaling. For example, it is common to have352×240 sized images (typical MPEG-1 size). In this case, it would beunnecessary to do any decimation to provide a ¼ scaling. For referenceframes, the motion compensation unit is required to write the full-sizedmacroblock to the reference frame buffer in memory, and then to thedisplay frame buffer in memory, since the display process is onlyoperating on the display frame buffer during scaling.

[0100] For the same image size to be reduced to {fraction (1/16)}scaling, there would need to be a decimation step. Once again, there isan exception in this case.

[0101] One of the objects of the scaling feature is to removeinterlacing artifacts. On true MPEG-1 images, there is no interlacingsince the pictures are exclusively frame encoded. MPEG-2 can allowinterlaced pictures of the same resolution (352×240) and the decimatoronly uses the top field picture to create the scaled macroblock. Thebottom field is discarded. Therefore, for a reference picture, the MCUwould be required to write the macroblock for the top field picture toboth the reference frame buffer and display buffer. For B pictures, theMCU would only need to write the top field picture into the displayframe buffer.

[0102] The video decode system in accordance with the present inventionprovides smooth transitions when entering and exiting small picturemode. Since frame buffer 2 is used for capture and display of smallpicture images (including reference and B pictures) when in videoscaling mode, care must be taken to prevent interference between thedecode and display processes at the time of display format switching.Also, there is a latency adjustment of one field time that must takeplace during the transition. Normal display modes have a 1.5 framelatency between decoding and displaying reference pictures, and a 0.5frame latency for B pictures. In small picture mode, the reference framelatency is changes to two frames and the B frame latency is changed toone frame.

[0103] For the display format change to occur seamlessly, the displaymust not be in the process of displaying a B picture when the transitionoccurs, otherwise the picture will appear disturbed. Therefore,transition must take place when a reference picture is being displayed.This is forced to happen by the microcode during a sequence header, whenthe first frame of the new sequence is a reference frame, and thedisplay is acting on the last frame of a previous sequence.

[0104] During the transition into and out of small picture mode, thehardware must make the adjustment in latency without disturbing thedecode or display process. Frame sync must be adjusted to the new mode.Further, field parity must be maintained. As a result of making theadjustment into small picture mode, a delay of one frame time isintroduced, which may effect PTS comparison. Subsequently, a skippedframe may be required in order to make up the time difference. This onlyoccurs when entering small picture mode. When leaving small picturemode, there is no loss of synchronization. The transition could alsocome at a time when a picture is already being skipped or repeated.

[0105] Referring to FIG. 9, the display format change signal is writtenasynchronously by the host. The format is received as a control signalinto a display format register 310, and microcode waits until processingthe sequence header before writing the information into display formatregister 310. This information is then seen by sync generator 300, aswell as register stages 330, 340 and 360. Register stage 1 330 capturesthe information at the next frame sync. Decode processes use the stage 1register 330, and the display processes use the stage 3 register 360.

[0106] Field counter 320 simply counts down from a starting number offields in a frame to a value of 1, and then repeats. Counter 320 isloaded by sync generator 300 via a control signal as shown. Syncgenerator 300 also receives the VSYNC signal, as well as the output ofstage 1 register 330. Sync generator 300 creates three signals, namely,a “frame sync” signal, a “new picture” signal and a “block video”signal. The “frame sync” signal indicates to the decode process when tobegin decoding a new frame. The “new picture” signal indicates to thedisplay process when to begin displaying a new frame. “Block video” isused to selectively suppress one frame of video image during transitionof the video decode system from a normal frame to a scaled frame. Theframe sync and new picture signals are pulses that are created onceevery two field times. In normal mode, the signals are 180° out ofphase, but in scaling mode (in accordance with this invention) thesignals are in phase. This is described further below in connection withthe flowchart of FIG. 10.

[0107] In all cases involving a switch into scaled picture mode, thereis a repeated frame which is blocked from view at the display. The blockis necessary due to buffer conflicts between the current reference frameand the reference frame that is currently being displayed. When video isblocked, the output of the decoder can be forced to a background color,such as black.

[0108] The latency adjustment is performed as soon as the stage 1register changes. There is an absence of a frame sync which allows thecurrent display frame to be scheduled to repeat. The sync generator thenadjusts the frame sync to occur in phase with the new picture, causingthe latency adjustment. During the repeated reference frame, the videois blocked for one frame time.

[0109]FIG. 10 is a flowchart of one embodiment of processing implementedby sync generator 300 (FIG. 9).

[0110] With initiation 600, processing waits for a VSYNC signal 610representative of the start of a new field. Upon receipt of the VSYNCsignal, processing generates a “new picture” sync signal and inquireswhether the field is being repeated based on received MPEG-2 syntax 630.The initial field counter (FC) value depends upon whether the field isto be repeated. If 3:2 pulldown is employed then the initial value ofthe field counter is 3 640, otherwise normal interlace is desired andthe field counter is loaded with a value of 2.

[0111] Once the field counter is set, processing inquires whetherscaling is to be implemented 650 and 670, respectively. If no, then thedecode system is in non-scaling or normal video mode. In this case,processing waits for a next VSYNC signal 680 and then inquires whetherthe field count equals two 690. If no, (e.g., because the field counterwas loaded with a value 3), the field counter is decremented 710 andprocessing waits for a next VSYNC signal 680. Once the field countequals 2, the “frame sync” signal is generated 700, after which thefield count is decremented 710 and processing determines whether thefield count value now equals 1 720. If the value equals 1, processinggenerates a “new picture” signal 620 after waiting for a new VSYNC 610.

[0112] Assuming scaling mode is desired, then processing proceeds frominquiry 650 or 670 to wait for a next VSYNC 730, after whichdetermination is made whether the field count equals 1 740. If no, thefield counter is decremented and processing returns to wait for a nextVSYNC 730. If the field count value is 1, then a new picture sync signalis generated 750. Thereafter, the field counter is loaded with a valueof 2 and the block video signal is generated 760. Again, the block videosignal is output from the sync generator to the display output interface(see FIG. 5) for blocking of a next frame of video.

[0113] After sending the block video signal, processing enters a steadystate, video scaling subprocess beginning by waiting for a next VSYNCsignal 780, after which processing determines whether the field countequals 1 790. If no, processing inquires whether the field count equals2 840, and again if no, processing decrements the field counter 860 andreturns to wait for the next VSYNC signal 780. Otherwise, adetermination is made as to whether the scaling command has now beenturned off by the host system 850. If no, the field counter isdecremented and processing waits for a next VSYNC signal 780. If thescaling mode has been switched off, then the field counter isdecremented at instruction 710 in the non-scaling process describedabove.

[0114] If the field count equals 1 at inquiry 790, then processinggenerates both the “new picture” signal and the “frame sync” signal inthe same phase. Again, to implement scaling it is necessary to changethe latency between the decode process and the display process from oneand a half frame times to two frame times for reference pictures, makingthe new picture signal and frame sync signal in phase. Processing thendetermines whether the MPEG-2 repeat field is set 810 to decide whetherto load the field counter with a value of 2 830 or 3 820 depending uponwhether normal interlacing or 3:2 pulldown is desired. This is necessaryeven though an adjustment in latency is made in order to accommodate anytype of frame rate conversion. After setting the field counter,processing returns to wait for a next VSYNC signal 780.

[0115] Those skilled in the art will note from the above discussion thatin order to implement smooth switching between normal mode and scaledvideo mode it is necessary to pass through a transitional phase beforereaching the steady state scaling process. Further, it is necessary toadjust the frame sync signal to occur within the same phase as the newpicture signal.

[0116] The present invention can be included, for example, in an articleof manufacture (e.g., one or more computer program products) having, forinstance, computer usable media. This media has embodied therein, forinstance, computer readable program code means for providing andfacilitating the capabilities of the present invention. The articles ofmanufacture can be included as part of the computer system or soldseparately.

[0117] Additionally, at-least one program storage device readable bymachine, tangibly embodying at least one program of instructionsexecutable by the machine, to perform the capabilities of the presentinvention, can be provided.

[0118] The flow diagrams depicted herein are provided by way of example.There may be variations to these diagrams or the steps (or operations)described herein without departing from the spirit of the invention. Forinstance, in certain cases, the steps may be performed in differingorder, or steps may be added, deleted or modified. All of thesevariations are considered to comprise part of the present invention asrecited in the appended claims.

[0119] While the invention has been described in detail herein inaccordance with certain preferred embodiments thereof, manymodifications and changes therein may be effected by those skilled inthe art. Accordingly, it is intended by the appended claims to cover allsuch modifications and changes as fall within the true spirit and scopeof the invention.

1. An integrated video decoding system comprising: a video decoder fordecoding an encoded stream of video data, said video decoder producing adecoded stream of video data; and a decimation unit coupled to saidvideo decoder and adapted to selectively scale said decoded stream ofvideo data for display.
 2. The video decoding system of claim 1, whereinsaid video decoding system further comprises a frame buffer, and whereinsaid decimation unit comprises means for scaling said decoded stream ofvideo data prior to storage thereof in said frame buffer.
 3. The videodecoding system of claim 2, wherein said frame buffer comprises multipledefined memory areas for receiving I, P & B frames of said decodedstream of video data, said multiple defined memory areas comprising afirst area and a second area for receiving full size I and P frames ofsaid decoded stream of video data, and at least one third area forreceiving scaled I, P & B frames of said decoded stream of video datacommensurate with said first area and said second area receiving saidfull size I and P frames.
 4. The video decoding system of claim 3,wherein said at least one third area comprises at least three areas,said at least three areas receiving said scaled I, P & B frames of saiddecoded stream of video data commensurate with said first area and saidsecond area receiving said full size I and P frames of said decodedstream of video data.
 5. The video decoding system of claim 2, whereinsaid frame buffer comprises memory of predefined size, and wherein saidvideo decoding system further comprises a normal video mode fordisplaying said decoded stream of video data without scaling, and ascaled video mode for scaling said decoded stream of video data prior todisplay, and wherein said video decoding system further comprises framebuffer pointer control logic for partitioning said memory of predefinedsize into multiple buffer areas when said video decoding system is insaid normal video mode, wherein said multiple buffer areas comprise atleast three buffer areas for receiving decoded I, P & B frames of saiddecoded stream of video data, and wherein said frame buffer pointercontrol logic comprises means for partitioning said memory of predefinedsize into at least five buffer areas when said video decoding system isin said scaled video mode, said at least five buffer areas comprising afirst area and a second area for receiving full size I and P frames ofsaid decoded stream of video data, and at least a third area, a fourtharea and a fifth area for receiving scaled I, P & B frames of saiddecoded stream of video data.
 6. The video decoding system of claim 5,wherein said decimation unit comprises means for performing B framememory reduction only on said decoded stream of video data when saidvideo decoding system is in said normal video mode, said B frame memoryreduction being performed prior to storage of each B frame of saiddecoded stream of video data in said frame buffer.
 7. The video decodingsystem of claim 1, wherein said video decoding system further comprisesa frame buffer, and wherein said decimation unit comprises means forscaling said decoded stream of video data prior to storage thereof insaid frame buffer, and wherein said video decoding system furthercomprises a normal video mode and a scaled video mode, and wherein saiddecimation unit is adapted to scale said decoded stream of video datafor display when in said scaled video mode.
 8. The video decoding systemof claim 7, wherein said decimation unit is adapted to perform B framememory reduction only on said decoded stream of video data prior tostorage for each B frame in said frame buffer when said video decodingsystem is in said normal video mode.
 9. The video decoding system ofclaim 7, further comprising display mode switch logic for switchingbetween said normal video mode and said scaled video mode, wherein saidswitching occurs without perceptual degradation of the display.
 10. Thevideo decoding system of claim 9, wherein said display mode switch logiccomprises means for blocking a frame of video from said display whenswitching between said normal video mode and said scaled video mode. 11.The video decoding system of claim 10, wherein said display mode switchlogic comprises a sync generator, said sync generator outputting a “newpicture” signal and a “frame sync” signal, and wherein said syncgenerator comprises means for outputting said new picture signal andsaid frame sync signal in different phase when in said normal videomode, and means for outputting said new picture signal and said framesync signal in phase when in said scaled video mode.
 12. The videodecoding system of claim 9, wherein a frame of said decoded stream ofvideo data includes an MPEG-2 repeat field signal, and wherein saiddisplay mode switch logic comprises means for ignoring said MPEG-2repeat field signal when decoding said frame simultaneous with switchingbetween said normal video mode and said scaled video mode.
 13. The videodecoding system of claim 9, wherein said video decoder comprises adecode process, and wherein said display comprises a display process,and said display mode switch logic comprises means for changing alatency between said decode process and said display process whenswitching between said normal video mode and said scaled video mode,said changing of said latency ensuring that said decoded stream of videodata is accommodated within said frame buffer when in said scaled videomode.
 14. The video decoding system of claim 1, wherein said decimationunit's scaling of said decoded stream of video data comprises at leastone of one-quarter or one-half frame reduction.
 15. A digital videodecoding system comprising: a video decoder for decoding an encodedstream of video data, said video decoder producing therefrom a decodedstream of video data; a video scalar for scaling said decoded stream ofvideo data prior to storage thereof in a frame buffer, wherein saidvideo decoding system comprises a normal video mode and a scaled videomode, said video scalar scaling said decoded stream of video data whensaid digital video decoding system is in said scaled video mode; anddisplay mode switch logic for switching between said normal video modeand said scaled video mode, wherein said switching occurs withoutperceptual degradation of a video display of said decoded stream ofvideo data.
 16. The digital video decoding system of claim 15, whereinsaid display mode switch logic includes logic for blanking said videodisplay for a defined period of time when switching between said normalvideo mode and said scaled video mode.
 17. The digital video decodingsystem of claim 16, wherein said predefined period of time for blankingsaid video display comprises one frame time of the digital videodecoding system.
 18. The digital video decoding system of claim 15,wherein said video scalar comprises a decimation unit coupled to saidvideo decoder and adapted to scale said decoded stream of video dataprior to storage thereof in said frame buffer when said digital videodecoding system is in said scaled video mode, said decoded stream ofvideo data comprising I, P & B frames and said decimation unit beingadapted to scale said I, P & B frames prior to storage thereof in saidframe buffer.
 19. The digital video decoding system of claim 18, whereinsaid decimation unit is further adapted to perform B frame memoryreduction only of said decoded stream of video data prior to storage ofB frames thereof in said frame buffer when said digital video decodingsystem is in said normal video mode.
 20. The digital video decodingsystem of claim 18, wherein said video decoder comprises a decodeprocess and said video display comprises a display process, and whereinsaid decode process and said display process have a first latency whenin said normal video mode, and a second latency when in said scaledvideo mode, and wherein said display mode switch logic comprises meansfor switching between said first latency and said second latency whenswitching between said normal video mode and said scaled video mode. 21.The digital video decoding system of claim 20, wherein said display modeswitch logic comprises a sync generator, said sync generator comprisingmeans for ignoring an MPEG-2 repeat field signal of a frame of said I, P& B frames being processed when switching between said normal video modeand said scaled video mode.
 22. The digital video decoding system ofclaim 21, wherein said sync generator outputs a “new picture” signal anda “frame sync” signal for use in retrieving from said frame buffer anddisplaying said decoded stream of video data, wherein said syncgenerator outputs said new picture signal and said frame sync signal inphase when said digital video decode system is in said scaled videomode.
 23. The digital video decoding system of claim 18, wherein saidframe buffer comprises multiple defined memory areas for receiving I, P& B frames of said decoded stream of video data, said multiple definedmemory areas comprising a first area and a second area for receivingunscaled I and P frames of said decoded stream of video data, and atleast one third area for receiving scaled I, P & B frames of saiddecoded stream of video data commensurate with the first area and thesecond area receiving said unscaled I and P frames.
 24. The digitalvideo decoding system of claim 23, wherein said unscaled I and P framescomprise full size I and P frames, and wherein said scaled I, P & Bframes comprise a fractional size of said full size I and P frames, saidfractional size comprising at least one of one-quarter or one-half saidfull size.
 25. A digital video decoding system comprising: a normalvideo mode and a scaled video mode, wherein when in said normal videomode, full size frames are output for display on a video display coupledto said digital video decoding system and when in scaled video mode,scaled frames comprising a fractional size of said full size frames areoutput for display on said video display; a frame buffer for temporarilystoring said full size frames and said scaled frames after a decodingtime thereof and prior to a display time thereof, wherein there is apredefined latency between said decoding time and said display time; andwherein said predefined latency between said decoding time and saiddisplay time comprises a first latency when in normal video mode and asecond latency when in scaled video mode.
 26. The digital video decodingsystem of claim 25, wherein said decoded stream of video data comprisesan interlaced format, and said first latency comprises one and one halfframe times for reference frames, and said second latency comprises twoframe times for reference frames.
 27. The digital video decoding systemof claim 25, further comprising display mode switch logic for switchingbetween said normal video mode and said scaled video mode, wherein saidswitching occurs without perceptual degradation of said video display.28. The digital video decoding system of claim 27, wherein said displaymode switch logic includes logic for blanking said video display for apredefined period of time when switching between said normal video modeand said scaled video mode.
 29. The digital video decoding system ofclaim 27, wherein said display mode switch logic includes a syncgenerator, said sync generator including means for ascertaining duringsaid switching from normal video mode to scaled video mode whether anext frame to be displayed includes an MPEG-2 repeat field signal, andif so, for suppressing said MPEG-2 repeat field signal when displayingsaid next frame.
 30. The digital video decoding system of claim 25,wherein said frame buffer comprises multiple defined memory areas forreceiving I, P & B frames of a decoded stream of video data, saidmultiple defined memory areas comprising a first memory area and asecond memory area for receiving full size I and P frames of saiddecoded stream of video data, and when in said scaled video mode, atleast one third area for receiving scaled I, P & B frames of saiddecoded stream of video data commensurate with said first area and saidsecond area receiving said full size I and P frames.
 31. The digitalvideo decoding system of claim 30, further comprising a video decoderfor decoding an encoded stream of video data and producing therefromsaid decoded stream of video data, and a decimation unit coupled to saidvideo decoder and adapted to scale said decoded stream of video data forsaid video display when said digital video decoding system is in saidscaled video mode.
 32. A frame buffer for a digital video decodingsystem having video scaling capabilities, said frame buffer comprising:multiple defined memory areas for receiving I, P & B frames of a decodedstream of video data, said multiple defined memory areas comprising: (i)a first area and a second area for receiving full size I and P frames ofsaid decoded stream of video data; and (ii) at least one third area forreceiving scaled I, P & B frames of said decoded stream of video datacommensurate with said first area and said second area receiving saidfull size I and P frames.
 33. The frame buffer of claim 32, wherein saidat least one third area comprises at least three areas, said at leastthree areas receiving said scaled I, P & B frames of said decoded streamof video data.
 34. The frame buffer of claim 33, wherein said multipledefined memory areas comprise a predefined region of memory coupled tosaid digital video decoding system, wherein said full size I and Pframes of said decoded stream of video data are employed by a decodeprocess of said digital video decoding system and said scaled I, P & Bframes of said decoded stream of video data are employed by a displayprocess of said digital video decoding system when said digital videodecoding system is in a scaled video mode.
 35. A frame buffer for adigital video decoding system having video scaling capabilities, saidframe buffer comprising: memory associated with said digital videodecoding system, said memory being of a predefined size; control logicfor partitioning said memory of predefined size into three buffer areaswhen said digital video decoding system is in a normal video mode,wherein said three buffer areas receive full size I, P & B frames of adecoded stream of video data; and wherein said control logic is furtheradapted to partition said memory into at least five buffer areas whensaid digital video decoding system is in a scaled video mode, said atleast five buffer areas comprising a first area and a second area forreceiving full size I and P frames of said decoded stream of video data,and at least a third area, a fourth area and a fifth area for receivingscaled I, P & B frames of said decoded stream of video data.
 36. Amethod for processing an encoded stream of video data employing adigital video decoding system, said method comprising: decoding theencoded stream of video data to produce a decoded stream of video data;scaling the decoded stream of video data when the digital video decodingsystem is in a scaled video mode, said scaling producing a scaleddecoded stream of video data; and after said scaling, buffering saidscaled decoded stream of video data in a frame buffer to await displaythereof.
 37. The method of claim 36, further comprising displaying saidscaled decoded stream of video data upon retrieval from said framebuffer, wherein said decoding and said displaying occur in phase whensaid digital video decoding system is in said scaled video mode.
 38. Themethod of claim 37, wherein said decoding and said displaying occur outof phase when said digital video decoding system is in a normal videomode in which said decoded stream of video data does not undergo saidscaling.
 39. The method of claim 38, further comprising switchingbetween said normal video mode and said scaled video mode, saidswitching comprising transitioning said decoding and said displayingfrom out of phase in said normal video mode to in phase in said scaledvideo mode.
 40. The method of claim 39, wherein said switching includesblanking said display for one frame time when transitioning between saidnormal video mode and said scaled video mode.
 41. The method of claim39, wherein said switching between said normal video mode and saidscaled video mode comprises delaying switching until said display isdisplaying a reference frame of said decoded stream of video data. 42.The method of claim 36, wherein said decoded stream of video datacomprises I, P & B frames, and wherein said scaling comprises scalingsaid I, P & B frames when said digital video decoding system is in saidscaled video mode.
 43. The method of claim 42, wherein said bufferingcomprises buffering unscaled I and P frames in said frame buffercommensurate with buffering scaled I, P & B frames when in said scaledvideo mode.
 44. The method of claim 43, further comprising performing Bframe memory reduction only on said decoded stream of video data whensaid digital video decoding system is in a normal video mode, said Bframe memory reduction on said decoded stream of video data beingperformed prior to buffering of said decoded stream of video data insaid frame buffer.
 45. The method of claim 36, wherein said digitalvideo decoding system includes a normal video mode, and said methodcomprises switching between said normal video mode and said scaled videomode, and wherein said switching comprises ignoring an MPEG-2 repeatfield signal of a frame of the decoded stream of video data beingprocessed for display when switching between said normal video mode andsaid scaled video mode.
 46. A method for processing an encoded stream ofvideo data employing a digital video decoding system having a normalvideo mode and a scaled video mode, said method comprising: decoding theencoded stream of video data to produce a decoded stream of video data;scaling, when in said scaled video mode, the decoded stream of videodata prior to storage thereof in a frame buffer; and switching betweensaid normal video mode and said scaled video mode without perceptualdegradation of a video display of said decoded stream of video data. 47.The method of claim 46, wherein said switching includes blanking saidvideo display for at least one frame time when transitioning betweensaid normal video mode and said scaled video mode.
 48. The method ofclaim 46, further comprising decimating, when in said normal video mode,the decoded stream of video data prior to storage thereof in a framebuffer, said decimating comprising performing B frame memory reductiononly on said decoded stream of video data.
 49. The method of claim 46,wherein said switching comprises ignoring an MPEG-2 repeat field signalof a frame of the decoded stream of video data being processed fordisplay when switching between said normal video mode and said scaledvideo mode.
 50. The method of claim 46, further comprising displayingsaid decoded stream of video data upon retrieval from said frame buffer,wherein said decoding and said displaying occur in phase when saiddigital video decoding system is in said scaled video mode, and saiddecoding and said displaying occur out of phase when said digital videodecoding system is in said normal video mode.
 51. A method forprocessing an encoded stream of video data employing a digital videodecoding system having a normal video mode and a scaled video mode, saidmethod comprising: decoding the encoded stream of video data to producea decoded stream of video data; buffering the decoded stream of videodata; displaying the buffered decoded stream of video data; andcontrolling said displaying and said decoding such that there exists afirst latency between decoding time and displaying time for a frame whensaid digital video decoding system is in said normal video mode and asecond latency between decoding time and display time for a frame whensaid digital video decoding system is in said scaled video mode.
 52. Themethod of claim 51, wherein said decoded stream of video data comprisesan interlaced format, and wherein said first latency comprises one andone half frame times for reference frames, and said second latencycomprises two frame times for reference frames.
 53. The method of claim51, further comprising switching between said normal video mode and saidscaled video mode, said switching including changing between said firstlatency and said second latency of decoding time to display time,wherein said switching occurs without perceptual degradation of thedisplay of said decoded stream of video data.
 54. The method of claim53, wherein said switching includes blanking said display for apredefined period of time when switching between said normal video modeand said scaled video mode.
 55. The method of claim 54, wherein saidswitching comprises ascertaining when switching from normal video modeto scaled video mode whether a next frame to be displayed includes anMPEG-2 repeat field signal, and if so, suppressing said MPEG-2 repeatfield signal when displaying said next frame.
 56. The method of claim51, wherein said buffering comprises buffering the decoded stream ofvideo data in a frame buffer comprising multiple defined memory areasfor receiving I, P & B frames of said decoded stream of video data, saidbuffering comprising, when in said scaled video mode, buffering fullsize I and P frames of said decoded stream of video data commensuratewith buffering scaled I, P & B frames of said decoded stream of videodata.
 57. A method for allocating a frame buffer for a digital videodecoding system having video scaling capabilities, said methodcomprising: partitioning the frame buffer into multiple memory areas forreceiving I, P & B frames of a decoded stream of video data, saidpartitioning comprising: defining a first area and a second area forreceiving full size I and P frames of said decoded stream of video data,and defining at least one third area for receiving scaled I, P & Bframes of said decoded stream of video data commensurate with the firstarea and the second area receiving the full size I and P frames.
 58. Amethod for allocating a frame buffer for a digital video decoding systemhaving video scaling capabilities, said method comprising: partitioningthe frame buffer into three buffer areas when said digital videodecoding system is in a normal video mode, wherein said three bufferareas receive full size I, P & B frames of a decoded stream of videodata; and partitioning said frame buffer into at least three bufferareas when said digital video decoding system is in a scaled video mode,said at least three buffer areas comprising a first area and a secondarea for receiving full size I and P frames of said decoded stream ofvideo data, and at least one third area for receiving scaled I, P & Bframes of said decoded stream of video data.
 59. The method of claim 58,wherein said at least one third area comprises at least a third area, afourth area and a fifth area for receiving said scaled I, P & B framesof said decoded stream of video data, wherein said at least third area,fourth area and fifth area each comprise less area than said first areaor said second area.
 60. An article of manufacture comprising: acomputer program product comprising a computer usable medium havingcomputer readable program code means therein for use in processing anencoded stream of video data employing a digital video-decoding system,said computer readable program code means in said computer programproduct comprising: computer readable program code means for causing acomputer to effect decoding the encoded stream of video data to producea decoded stream of video data; computer readable program code means forcausing a computer to effect scaling the decoded stream of video datawhen the digital video decoding system is in a scaled video mode, saidscaling producing a scaled decoded stream of video data; and computerreadable program code means for causing a computer to effect bufferingsaid scaled decoded stream of video data in a frame buffer to awaitdisplay thereof.
 61. An article of manufacture comprising: a computerprogram product comprising a computer usable medium having computerreadable program code means therein for use in processing an encodedstream of video data employing a digital video decoding system having anormal video mode and a scaled video mode, said computer readableprogram code means in said computer program product comprising: computerreadable program code means for causing a computer to effect decodingthe encoded stream of video data to produce a decoded stream of videodata; computer readable program code means for causing a computer toeffect scaling the decoded stream of video data prior to storage thereofin a frame buffer when said digital video decoding system is in saidscaled video mode; and computer readable program code means for causinga computer to effect switching between said normal video mode and saidscaled video mode without perceptual degradation of a video display ofsaid decoded stream of video data.
 62. An article of manufacturecomprising: a computer program product comprising a computer usablemedium having computer readable program code means therein for use inprocessing an encoded stream of video data employing a digital videodecoding system having a normal video mode and a scaled video mode, saidcomputer readable program code means in said computer program productcomprising: computer readable program code means for causing a computerto effect decoding the encoded stream of video data to produce a decodedstream of video data; computer readable program code means for causing acomputer to effect buffering the decoded stream of video data; computerreadable program code means for causing a computer to effect displayingthe buffered decoded stream of video data; and computer readable programcode means for causing a computer to effect controlling said displayingand said decoding such that there exists a first latency betweendecoding time and displaying time for a frame when said digital videodecoding system is in said normal video mode and a second latencybetween decoding time and display time for a frame when said digitalvideo decoding system is in said scaled video mode.
 63. An article ofmanufacture comprising: a computer program product comprising a computerusable medium having computer readable program code means therein forallocating a frame buffer for a digital video decoding system havingvideo scaling capabilities, said computer readable program code means insaid computer program product comprising: computer readable program codemeans for causing a computer to effect partitioning the frame bufferinto multiple memory areas for receiving I, P & B frames of a decodedstream of video data, said computer readable program code means forcausing a computer to effect partitioning comprising: (i) computerreadable program code means for causing a computer to effect defining afirst area and a second area for receiving full size I and P frames ofsaid decoded stream of video data, and (ii) computer readable programcode means for causing a computer to effect defining at least one thirdarea for receiving scaled I, P & B frames of said decoded stream ofvideo data commensurate with said first area and said second areareceiving the full size I and P frames.
 64. An article of manufacturecomprising: a computer program product comprising a computer usablemedium having computer readable program code means therein for use inallocating a frame buffer for a digital video decoding system havingvideo scaling capabilities, said computer readable program code means insaid computer program product comprising: computer readable program codemeans for causing a computer to effect partitioning the frame bufferinto three buffer areas when said digital video decoding system is in anormal video mode, wherein said three buffer areas receive full size I,P & B frames of a decoded stream of video data; and computer readableprogram code means for causing a computer to effect partitioning saidframe buffer into at least three buffer areas when said digital videodecoding system is in a scaled video mode, said at least three bufferareas comprising a first area and a second area for receiving full sizeI and P frames of said decoded stream of video data, and at least onethird area for receiving scaled I, P & B frames of said decoded streamof video data.